A 1.5V 200ms/s 13b 25mw DAC with Randomized Nested Background Calibration in 0.13μm CMOS.

Martin Clara,Wolfgang Klatzer,Berthold Seger,Antonio Di Giandomenico,Luca Gori

Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference（2007）

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摘要

Time-domain randomization of the unit current-cell refresh period converts the tonal behavior of cyclic background calibration into noise. Together with nested calibration of all DAC-segments a low-frequency SFDR of 83.7dB is achieved. The chip is fabricated in a standard 0.13mum CMOS process. Clocked at 200MHz, it consumes 25mW from a 1.5V supply.

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关键词

CMOS integrated circuits,calibration,digital-analogue conversion,0.13 micron,1.5 V,13 bit,200 MHz,25 mW,CMOS process,DAC,cyclic background calibration,randomized nested background calibration,time-domain randomization,tonal behavior

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