Smallest Bit-Line Contact Of 76nm Pitch On Nand Flash Cell By Using Reversal Pr (Photo Resist) And Sadp (Self-Align Double Patterning) Process

For the scaling down of design rule to develop the high density NAND Flash device, the reduced active area forces to form a small bit-line contact with the low contact-resistance, as well as the low junction leakage current due to the borderless contact. In this paper, we propose a novel process to make 38nm small size contact with 76nm pitch by using the reversal PR (Photo Resist) and SADP (Self-Align Double patterning) process. The methods to minimize the contact resistance and to suppress the junction leakage current were explained on NAND Flash device with 38nm node technology.