CAD Techniques for Power Optimization in Virtex-5 FPGAs

We consider dynamic power dissipation in FPGAs and present CAD techniques for dynamic power reduction. The proposed techniques, comprising power-aware placement, routing, and a novel post-routing transformation, are applied to optimize the power consumed by industrial designs implemented in the Xilinx R VirtexTM-5 FPGA. Board-level power measurements on a suite of industrial designs show that the techniques reduce power by 10%, on average. I. Introduction In more than 20 years since the introduction of the FPGA, re- search and development has produced dramatic improvements in FPGA speed and area efcienc y, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. Today, power consumption is a key concern for FPGA vendors and customers. Reducing the power of FPGAs is key to lowering packaging and cool- ing costs, improving device reliability, and opening the door to new markets such as mobile electronics (1). Power dissipation in CMOS circuits comprises both static (leakage) power and dynamic power. Dynamic power is caused by transitions on the signals of a circuit and is gov- erned by the equation (2): Pavg = 1 2 X