Enhanced Stress Proximity Technique with Recessed S/D to Improve Device Performance at 45nm and Beyond

Shyue Seng Tan,S Fang,Junying Yuan, Linjing Zhao,Young Min Lee, J J Kim, Robert J Robinson, Jiang Yan,Jongho Park,Michael P Belyansky, Jianye Li, R Stierstorfer,S D Kim,Nivo Rovedo, Hong Shang,Hioktiaq Ng,Y Li,John Sudijono,Elgin Quek, Sheng Chu,R Divakaruni,S Sundar Kumar Iyer

Hsinchu（2008）

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摘要

A novel low cost technique to improve device performance by enhanced stress proximity technique (eSPT) with recessed S/D (ReSD) has been demonstrated for the first time. pFET performance improvement of 40% was demonstrated with eSPT. pFET performance with Ion of 520 uA/um at Ioff of InA/um was achieved with the low cost processes. With optimized eSPT, 15% improvement in ring delay has been demonstrated.

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关键词

field effect transistors,enhanced stress proximity technique,low cost processes,pfet,ring delay,stress proximity technique,device performance,recessed s/d,spt,stress,espt,cmos technology,dsl,microelectronics

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