A Low-Power mmWave CML Prescaler in 65nm SOI CMOS Technology

Daeik Daniel Kim,Choongyeun Cho,Jonghae Kim,J O Plouchart,Daihyun Lim

Monterey, CA（2008）

引用 5|浏览15

暂无评分

摘要

A 5-stage CML prescaler operating up to 84 GHz is presented. The prescaler requirements, design considerations, simulations, and performance measurements are presented. The first divide-by-2 stage consumes 17.7mW at 1.8V, or 26.40 power-delay product per gate. The prescaler's phase noise gain degeneration at the sensitivity curve boundary is reported for the first time.

查看译文

关键词

cmos integrated circuits,low-power electronics,millimetre wave circuits,prescalers,soi cmos technology,low-power mmwave cml prescaler,power 17.7 mw,voltage 1.8 v,phase locked loops,low power electronics,gain,oscillators,cmos technology,phase noise

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要