3D chip package interaction thermo-mechanical challenges: Proximity effects of Through Silicon vias and μ-bumps

Weida Guo,G Van Der Plas,A Ivankovic,G Eneman,V Cherman,B De Wachter,A Mercha,Mireia Bargallo Gonzalez,Yann Civale,A Redolfi,T Buisson, A Jourdan,Bart Vandevelde,K J Rebibis,I De Wolf,A La Manna,G Beyer,Eric Beyne,B Swinnen

ICICDT（2012）

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摘要

The 3D IC stacking technology with Through Silicon via (TSV) approach promises lower cost, smaller footprint and higher performance for heterogeneous system integration. 3D integration technology needs key components to be enabled: Like TSV technology, Wafer thinning, thin wafer carrier and handling technology and μbumps interconnects. In the via-middle 3D-Stacked IC approach, Cu filled TSVs are integrated after device fabrication and before metal 1. The stress patterns around TSV's and μbumps are considered as important concerns for 3D integration, as this leads to additional variability in MOSFET mobility, threshold voltage, and drivability. This contribution reviews the assessment of TSV and μbumps proximity effects on FEOL device performance.

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关键词

mosfet,integrated circuit interconnections,integrated circuit packaging,three-dimensional integrated circuits,μ-bumps interconnects,3d ic stacking technology,3d chip package interaction,3d integration technology,feol device performance,mosfet mobility,tsv technology,device fabrication,drivability,handling technology,heterogeneous system integration,proximity effect,stress pattern,thermo-mechanical challenge,thin wafer carrier,threshold voltage,through silicon via,wafer thinning,μbump,3d ic,cmos,tsv,keep out zone,mechnical stress,silicon,chip,stress

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