Plasma etch and low temperature PECVD processes for via reveal applications
Electronic Components and Technology Conference（2012）
摘要
This paper will focus on 300mm etch and CVD technologies for via reveal (VR) processing. Data on silicon etching will show that etch rates >;5μm/min, with uniformity ±2.5% and selectivity to the liner oxide around ~200:1 can be achieved on bonded TSV wafers. A novel end-point detection method will also be presented allowing control of the reveal height. The ability to tune the uniformity from centre fast to edge fast will also be covered. A range of stable, repeatable, dielectric films will be presented having a deposition temperature <;180°C and no moisture uptake. These films will also be shown to have highly conformal via tip coverage and excellent electrical properties, with breakdown voltages >;10 MV/cm and leakage current densities <;1E-9 A/cm2 at 2MV/cm.
更多查看译文
关键词
dielectric thin films,electric breakdown,elemental semiconductors,leakage currents,plasma CVD,silicon,three-dimensional integrated circuits,Si,bonded TSV wafers,breakdown voltages,deposition temperature,dielectric films,electrical properties,end-point detection,leakage current densities,low temperature PECVD process,plasma etch,silicon etching,via reveal processing,wavelength 300 nm,
AI 理解论文
溯源树
样例
生成溯源树，研究论文发展脉络
Chat Paper
正在生成论文摘要