6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs

Yibo Liao,Menghsueh Chiang,Nattapol Damrongplasit,Tsujae King Liu,Weichou Hsu

VLSI Technology, Systems, and Applications（2013）

引用 11|浏览2

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摘要

6T-SRAM cell design with gate-all-around (GAA) silicon nanowire (NW) MOSFETs is investigated via three-dimensional TCAD simulations and compact analytical modeling. A rectangular NW channel design allows the transistor width to be adjusted with reduced impact on short-channel effects. This in turn provides a means for tuning the cell ratios to optimize the tradeoff between static noise margin and writeability with optimal cell layout area efficiency.

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关键词

mosfet,sram chips,electronic engineering computing,elemental semiconductors,nanowires,silicon,technology cad (electronics),6-t sram cell design,gaa silicon nanowire mosfet,si,gate-all-around silicon nanowire mosfet,optimal cell layout area efficiency,rectangular nw channel design,short-channel effects,static noise margin,three-dimensional tcad simulations,transistor,writeability,solid modeling,semiconductor device modeling,logic gates

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