A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS

VLSI Circuits(2013)

Cited 35|Views74
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Abstract
A 5.4GS/s 12b 2-way interleaved pipeline ADC is presented. To achieve high speed, a complementary switched-capacitor amplifier is proposed, along with ping-pong amplifier sharing and digital MDAC equalization. The ADC achieves 61dB SNR and 57dB THD up to 2.6GHz input frequency at 5.4GS/s, consumes 500mW and occupies 0.4mm2 area in 28nm CMOS.
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Key words
cmos analogue integrated circuits,amplifiers,analogue-digital conversion,equalisers,pipeline processing,switched capacitor networks,2-way interleaved pipeline adc,cmos,bit rate 5.4 gbit/s,complementary switched-capacitor amplifier,digital mdac equalization,noise figure 61 db,ping-pong amplifier sharing,power 500 mw,cmos integrated circuits,signal to noise ratio,topology,pipelines,switches
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