Unified compact modelling strategies for process and statistical variability in 14-nm node DG FinFETs

This paper presents a principal component analysis (PCA)-based unified compact modelling strategy for process-induced and statistical variability in 14-nm double gate SOI FinFET technology. There is strong interplay between process and statistical variability in FinFET technology and failure to capture the correlations between them can lead to an inaccurate estimation of overall statistical variability with errors of up to 30%. Therefore a new unified compact modelling strategy for variability, based on comprehensive atomistic simulations within the CD corner space, is presented. First, an extended uniform compact model is built to capture CD process variation using a set of parameters, and then statistical variability is extracted using another small set of `statistical' parameters. Later, the response of the extracted statistical parameters over the CD space is characterised, and finally used in a PCA method to generate the unified compact models capturing both process and statistical variability over the whole CD variation space.