A novel leakage power reduction technique for CMOS circuit design
SoC Design Conference（2010）
摘要
Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit types for low-power design centered around inserting controlling transistors between pull-up and pull down circuits as well as between pull-up circuits/pull down circuits and power/ground. We investigate the characteristics of proposed gate types in terms of ability to reduce power consumption and their associated delay overhead. In addition, several variations of drain gating are discussed. In the end, an overall procedure for low-power circuit design is proposed by intelligently mixing various proposed circuit types for gates in the circuits based upon gate criticality analysis. Extensive SPICE simulation results were reported using 45nm, 32nm and 22nm process technologies. Significant power reduction is achieved with zero or little increase in the critical path delay of the overall circuits.
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关键词
cmos integrated circuits,spice,integrated circuit design,low-power electronics,oxide coated cathodes,cmos circuit design,spice simulation,associated delay overhead,critical path delay,deep submicron process,drain gating,gate criticality analysis,gate types,high transistor density,leakage power reduction,low-power circuit design,low-power design,low-power techniques,oxide thickness,power consumption,pull down circuits,pull-up circuits,reduced voltage,size 22 nm,size 32 nm,size 45 nm,transistors,leakage power consumption,sleep transistors,transistor stacking,critical path,low power electronics,circuit design,logic gates,leakage current,threshold voltage
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