Suppression of threshold voltage shift for normally-Off GaN MIS-HEMT without post deposition annealing

Masahito Kanamura,Thomas Ohki,Shuji Ozaki,Masato Nishimori,Shuichi Tomabechi,Junji Kotani, T Miyajima,Norio Nakamura,Naoya Okamoto,Takamaro Kikkawa, Kunihiko Watanabe

Power Semiconductor Devices and ICs（2013）

引用 13|浏览2

暂无评分

摘要

In this paper, we present a method of reducing threshold voltage shift for normally-off GaN MIS-HEMT by the optimization of dielectric deposition conditions. High-temperature deposition of Al2O3 insulator decreases the impurities in a dielectric film, leading to small C-V and I-V hysteresis under large positive gate voltage operation. Moreover, Al2O3 deposited at high temperature achieve high quality interface and bulk without post deposition annealing (PDA), preventing the degradation of electrodes and crystallization of insulator film. The fabricated device shows small C-V and I-V hysteresis, with a breakdown voltage of greater than 600 V.

查看译文

关键词

iii-v semiconductors,alumina,crystallisation,dielectric thin films,gallium compounds,high electron mobility transistors,wide band gap semiconductors,al2o3,c-v hysteresis,gan,i-v hysteresis,dielectric deposition conditions,electrode degradation,high quality interface,high-temperature deposition,insulator film crystallization,normally-off mis-hemt,positive gate voltage operation,threshold voltage shift suppression,logic gates,hysteresis,insulators

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要