A versatile 30V analog CMOS process in a 0.18μm technology for power management application

Y Choi,Ilyong Park,Hyunchol Lim,Miyoung Kim,Chuljin Yoon,Namjoo Kim,Kwangdong Yoo,Lou N Hutter

Power Semiconductor Devices and ICs（2011）

引用 8|浏览8

暂无评分

摘要

A versatile 30V analog CMOS process in a 0.18 μm technology node has been developed by using cost-effective and modular fashion. To reduce the thermal budget deep NWELL isolation is formed after CMOS well formation. The drain-extended (DE) CMOS from 7V to 30V shows very competitive trade-off performance between the breakdown voltage and the specific on-resistance. In addition, low 1/f noise of 5V CMOS can be obtained by pure gate oxide process.

查看译文

关键词

1/f noise,cmos integrated circuits,low-power electronics,cmos well formation,analog cmos process,deep nwell isolation,drain-extended cmos,power management application,pure gate oxide process,size 0.18 mum,voltage 30 v,voltage 5 v,cost effectiveness,transistors,satisfiability,analog circuits,low power electronics,circuit design,logic gate,logic gates,noise,eprom,cmos technology,breakdown voltage,process development

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要