Performance Model For Mapping Processing Tasks To Openflow Switch Resources

In a recent effort to push forward the powerful concept of software defined networks, OpenFlow has gained a lot of popularity as a practical approach to split the data and the control planes by standardizing an open interface that allow remote software controllers to dictate the forwarding behavior of network devices. The latest flexible version 1.1 of OpenFlow is limited to software forwarding plane implementations. In order to deliver high performance, we implement an OpenFlow v1.1 hardware forwarding plane based on network processors. Delivering the optimal performance requires finding the optimal mapping of OpenFlow tasks to hardware resources which is already known as an NP-hard combinatorial problem. In our work, we propose a performance model that helps choose a better mapping without the burden of implementing and comparing all possible mappings on network processor. Our model assumes that the performance bottleneck of the hardware forwarding pipeline comes from the lookup tasks. This is generally the case of OpenFlow lookup tasks based on more than 14 tuple headers and requiring high latency external memories in order to provide a large number of possible flow entries. Our model, validated using real hardware implementations comparisons, shows that the lookup tasks that use the same external memories in the same pipeline are not worth parallelizing. In fact, mapping them to different parallel processing elements will only increase the response time of the lookup memory which will slow down the forwarding pipeline.