Low power SoCs with resonant dynamic logic using inductors for energy recovery

High speed dynamic logic implementations have power consumption bottlenecks when driving large capacitive loads that occur in clock trees, memory bit/word lines and I/O pads. This severely limits their use in a System on Chip (SoC) at Gigabit rates. A novel dynamic logic gate that saves switching power by 50% with LC resonance is described. The stored energy on the load capacitance is transferred using an inductor during logic evaluation and recovered back for pre-charge, rather than being wasted. Implementation in a standard 90nm CMOS process illustrates feasibility with realistic on-chip inductors. Inductor values below 5nH are sufficient to operate at 1GHz speed driving 1pF of load while consuming less than 1.1mW of power from a 1.8V supply, thus breaking the f.CV2 barrier. The savings are realized over a wider range of frequency and less sensitive to LC variations than previously reported.