A highly scalable 8-layer Vertical Gate 3D NAND with split-page bit line layout and efficient binary-sum MiLC (Minimal Incremental Layer Cost) staircase contacts

h y lue
h y lue
shihcheng huang
shihcheng huang
guanru lee
guanru lee
alfredtunghua chuang
alfredtunghua chuang

Electron Devices Meeting, 2012, Pages 2.3.1-2.3.4.

Cited by: 23|Bibtex|Views14|DOI:https://doi.org/10.1109/IEDM.2012.6478963
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Other Links: academic.microsoft.com

Abstract:

We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effectiv...More

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