An 11b 3.6gs/S Time-Interleaved Sar Adc In 65nm Cmos

Over the last years several low-power time-interleaved (TI) ADC designs in the 2.5-to-3.0GS/s range have been published [1-3], intended for integration in applications like radar, software-defined radio, full-spectrum cable modems, and multi-channel satellite reception. It is to be expected that future generations of these applications will require a higher ADC sampling rate, while maintaining good high-frequency linearity. Furthermore, a high spectral purity is desired, as spurs can cause an SNR degradation of several dB for weak narrowband signals. For interleaved converters, this mandates an output with limited interleaving artifacts. For the reception of broadband and multi-carrier signals, the gain mismatch and time-skew tones do not typically limit performance, since the spurs are evenly spread over frequency due to the broadband nature of the input signal. The offset mismatches, however, generate spurs at fixed frequencies, thereby representing the main performance limitation. This paper presents a prototype 3.6GS/s 11b TI SAR ADC with a THD that is better than -55dB at 2.5GHz and that has gain and offset spurs below -80dBFS, consuming 795mW in 65nm CMOS.