Fabrication and electrical characteristics of self-aligned (SA) gate-all-around (GAA) si nanowire MOSFETs (SNWFET)

Dongwon Kim,Kyoung Hwan Yeo,Sung Dae Suk,Ming Li,Yun Young Yeoh,Dong Kyun Sohn,Chilhee Chung

IC Design and Technology（2010）

引用 5|浏览10

暂无评分

摘要

We have proposed gate-all-around Silicon nanowire MOSFET (SNWFET) on bulk Si as an ultimate transistor. Well controlled processes are used to achieve gate length (LG) of sub-10nm and narrow nanowire widths. Excellent performance with reasonable VTH and short channel immunity are achieved owing to thin nanowire channel, self-aligned gate, and GAA structure. Transistor performance with gate length of 10nm has been demonstrated and nanowire size (DNW) dependency of various electrical characteristics has been investigated. Random telegraph noise (RTN) in SNWFET is studied as well.

查看译文

关键词

mosfet,elemental semiconductors,nanowires,random noise,silicon,transistors,snwfet,bulk si,electrical characteristic,gate-all-around silicon nanowire mosfet,nanowire size,random telegraph noise,self-aligned gate,thin nanowire channel,transistor,tin,immune system,resistance,fabrication,process control,etching,logic gates

AI 理解论文

溯源树

样例

生成溯源树，研究论文发展脉络

Chat Paper

正在生成论文摘要