Fabrication and electrical characterization of 5×50um through silicon vias for 3D integration

Bharat Bhushan,Minrui Yu,John O Dukovic,L Y Wong,Aksel Kitowski, Mun Kvu Park,Jingyu Hua, Shwetha Bolagond,Anthony C T Chan,Chin Hock Toh,Aditya Sundarrajan,Narendra Kumar,Sesh Ramaswami

Interconnect Technology Conference（2013）

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摘要

We present fabrication, electrical characterization, and metrology analysis results of 5×50um TSVs for 3D integration. Specifically, electrical performance of blind TSVs is evaluated by capacitance-voltage (CV) and current-voltage (IV) measurements. Important electrical parameters such as oxide capacitance, minimum TSV capacitance, leakage current, and breakdown voltage are extracted and show good results. The capacitance values also closely match model predictions. The electrical testing data are further verified with a variety of materials analysis techniques.

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关键词

capacitance,integrated circuit interconnections,leakage currents,three-dimensional integrated circuits,3d integration,breakdown voltage,capacitance-voltage measurements,current-voltage measurements,electrical testing data,leakage current,metrology analysis,minimum tsv capacitance,oxide capacitance,through silicon vias fabrication,fabrication,silicon

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