High-speed J-delayed & K-dimensional LFSR architecture in VLSI

This paper introduces a new framework to construct fast and efficient pseudo-random (PN) sequence generation for bit scrambling, called a J-delayed and K-dimensional Linear Feedback Shift Register (JKLFSR). In the proposed framework, we generate the state of a J-shifted LFSR using one clock and K-bit multiple outputs of a LFSR each clock cycle for scrambling/descrambling of large coded bits using an output of LFSR. JKLFSR is highly relevant for the scrambling/descrambling process for a high-speed mass data transmission in an LTE-Advanced system, as it has fast computation and supports clock-based processing. In addition, we show that JKLFSR has an efficient performance theoretically in generating PN sequences. H/W simulation results verify the validity of the theory and demonstrate that we reduced the processing time used for generating PN sequences from (J + DL) clocks to (1 + DL/K) clocks as compared with a conventional LFSR, where DL denotes the length of a data stream.