Fine-Feature Patterning Of Self-Aligned Polymeric Thin-Film Transistors Fabricated By Digital Lithography And Electroplating

Spatially controlled jet-printed etch masks, having a minimum drop size of 40-50 mu m, were used to define gap patterns having a minimum feature size of similar to 10 mu m. The defined gaps, in combination with nickel electroplating, were used to create bottom-gate electrode thin-film transistors (TFTs) with gate lengths of 10-20 mu m and gate widths of 150 mu m. Self-aligned source/drain top contacts were used for fabricating polythiophene-based TFT devices having channel width-to-length ratios of similar to 4. A typical p-channel TFT device had an on/off ratio of 10(7), threshold voltage of -1 V, and field-effect mobility of 0.034 cm(2)/V s. (c) 2006 American Institute of Physics.