Planar Dual Gate Oxide Ldmos Structures In 180nm Power Management Technology

Santosh Sharma,Theodore Letavic,Yun Shi, Alain Loiseau, John-Ellis Monaghan,Natalie Feilchenfeld, Rick Phelps, Christopher Lamothe, Don Cook,Jim Dunn, Georg Roerher, Helmut Nauschnig,Rainer Minixhofer

2012 24TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES AND ICS (ISPSD)(2012)

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摘要
This paper presents a 20V-rated planar dual gate oxide NLDMOS power device structure fabricated in a 180nm power management technology. The performance of the planar dual gate device structure is compared to a conventional STI-based device and it is shown that the planar dual gate structure has superior BVds-Rs(p), g(m), HCI reliability, and forward safe operating area figures-of-merit. The planar dual gate structure exhibits BVds=32V/14 m Omega.mm(2) specific on-resistance (and BVds= 20V/7.5m Omega.mm(2) for a drift length scaled version), hot carrier reliability in excess of 10 years analog lifetime in all bias regimes, and a linear forward IV characteristic. The planar dual gate architecture is scalable in rated voltage from 7V to 24V, and is an ideal component for the integration of USB switch, battery charging, backlighting, and PA envelope tracking mobile applications.
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关键词
LDMOS,dual gate oxide,forward safe operating area,hot carrier induced drift
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