Advanced Junction Profile Design Scheme By Low-Temperature Millisecond Annealing And Co-Implant For High Performance Cmos

We found that the relatively low temperature millisecond annealing at S/D activation for nFET is enhanced the co-implanted halo activation regardless of sequence of MSA and spike-RTA. Tilt-and-twist extension implantation technique with millisecond extension annealing for pFET was also per-formed to reduce the parasitic resistance. By combining these technique, an aggressively scaled high-performance bulk CMOS transistors with world competitive nFET and pFET drive currents of 1282/835 mu A/mu m at 100nA/mu m off-current at Vd = 1 V and Lg = 34 nm respectively, were developed with a conventional poly/SiON gate stack. The developed CMOS transistors not only have high-performance but also manufacturing friendly and cost-effective compared with metal/high-k stack devices.