Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods
Proceedings of SPIE, the International Society for Optical Engineering(2009)
摘要
For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography
presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years,
source optimization and mask pattern correction have been conducted as two separate RET steps. For source
optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not
considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been
introduced for the lithography development stage. The next important step would be the extension of SMO, and in
particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set
Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or
ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device
results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO
and its extendibility to full chip designs.
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关键词
semiconductors,semiconductor manufacturing,data storage,chip,level set method,optics,lithography
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