E-Beam Writing Time Improvement For Inverse Lithography Technology Mask For Full-Chip

Inverse Lithography Technology (ILT) is becoming one of the strong candidates for 32nm and below. ILT masks provide significantly better litho performance than traditional OPC masks. To enable ILT for production as one of the leading candidates for low-k(1) lithography, one major task to overcome is mask manufacturability including mask data fracturing, MRC constraints, writing time, and inspection. In prior publications([4,5]), it has been shown that the Inverse Synthesizer (IS (TM)) product has the capability to adjust for mask complexity to make it more manufacturable while maintaining the significant litho gains of nearly ideal ILT mask. The production readiness of ILT has been demonstrated at full-chip level. To fully integrate ILT mask into production, a number of areas were investigated to further reduce ILT mask complexity without compromising too much of process window. These areas include flexible controls of SRAF placements with respect to local feature sizes, separate control of Manhattan mask segment length of main and SRAF features, topology based variable segmentation length, and jog alignment. The impact of these approaches on e-beam mask writing time and lithography performance is presented in the paper.