Optimizing History Effects in 65nm PD-SOI CMOS

Q Liang,Tatsuo Kawamura,M B Ketchen,Shigeru Kawanaka,Mario M Pelella,David Robertson,Manjul Bhushan,Kevin Mcstay,G Freeman,Kazuhisa Miyamoto,Effendi Leobandung, S Huang

international soi conference（2006）

引用 3|浏览57

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摘要

History effects in 65-nm partially-depleted Silicon-on-Insulator CMOS technology are systematically measured and characterized. The impact of various process adjustments on these effects is analyzed, and an optimization strategy is presented. Hardware data show >9% history effect changes is controllable with no loss of performance (e.g. speed and leakage), offering more flexibility in SOI circuit designs.

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关键词

silicon on insulator,si,integrated circuit design,cmos integrated circuits,circuit design

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