A 5.1GHz 0.34mm2 Router for Network-on-Chip Applications

2007 IEEE Symposium on VLSI Circuits(2007)

引用 30|浏览96
暂无评分
摘要
A five-port two-lane pipelined packet-switched router core with phase-tolerant mesochronous links forms the key communication fabric for an 80-tile network-on-chip (NoC) architecture. The 15FO4 design combines 102 GB/s of raw bandwidth with low fall-through latency of 980 ps. A shared crossbar architecture with a double-pumped crossbar switch enables a compact 0.34 mm 2 router layout. In a 65nm eight-metal CMOS process, the router contains 210K transistors and operates at 5.1GHz at 1.2 V, while dissipating 945 mW.
更多
查看译文
关键词
network-on-chip,phase-tolerant mesochronous links,shared crossbar architecture,double-pumped crossbar switch,eight-metal CMOS process,five-port two-lane pipelined packet-switched router core,NoC architecture,frequency 5.1 GHz,time 980 ps,size 65 nm,voltage 1.2 V,power 945 mW
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要