A Delay Circuit For Build-Out-Self-Test In 0.18-Mu M Cmos

Li Tianmao, Hasimoto Toshifumi,Kuroki Yukinori

2007 INTERNATIONAL WORKSHOP ON ELECTRON DEVICES AND SEMICONDUCTOR TECHNOLOGY（2007）

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摘要

This paper describes a digital controlled delay circuit for BOST(build-out-self-test) with picosecond resolution. The proposed circuit operates at 250MHz under 1.8V supply according to Hspice simulation on the extracted layout. The complete design was fabricated in a standard TSMC 0.18 mu m CMOS process technology. The proposed circuit draws 7mw of static power and occupies an area of 0.09mm(2).

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关键词

CMOS integrated circuit, coarse, fine, phase locked loop, low-voltage design

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