The Design of a High Speed Low Power Phase Locked Loop
mag(2024)
摘要
The upgrade of the ATLAS Liquid Argon Calorimeter readout system calls for
the development of radiation tolerant, high speed and low power serializer
ASIC. We have designed a phase locked loop using a commercial 0.25 um
Silicon-on-Sapphire (SoS) CMOS technology. Post-layout simulation indicates
that tuning range is 3.79-5.01 GHz and power consumption is 104 mW. The PLL has
been submitted for fabrication. The design and simulation results are
presented.
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