Novel Cycling-induced Program Disturb of Split Gate Flash Memory
2007 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS - 45TH ANNUAL(2007)
摘要
Analytical program disturb modeling of split gate flash is presented for the first time and used to estimate post-cycling time to disturb by formulating punch through current evolution with cycling. The optimized erase voltage is chosen to achieve maximum endurance based on tradeoff of erase time pushout and post-cycling program disturb. The early punch through failure mechanism of array cycling is thus understood and eliminated by new-proposed STI corner shape
更多查看译文
关键词
split gate flash,endurance,program disturb,interface state
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要