Impacts of overlay correction model and metrology sampling scheme on device yield

As the feature sizes continue to shrink, more overlay metrology data are needed to meet tighter overlay specifications which ensure high device yield. This study investigates the advantages of process corrections to overlay errors using various reduced measurement wafer schemes, and the improvement in yield that is realized using optimized overlay correction models. The capacitor layer of a 4x node DRAM product is chosen for verifying the sampling schemes in the experiment, because overlay errors of this layer are sensitive to device yield. The test wafers are split into five groups; four groups are sampled using various schemes and overlay correction models, and one group has a programmed overlay error. The post-correction overlay residuals in full wafer, baseline sampling and optimized sampling agree closely with predictions that are based on raw measurements. A scheme with iHOPC (intrafield high order process correction) partial third-order terms with a CPE (correction per exposure) function provides the best overlay performance. The averaged device yields of reduced sampling schemes are comparable with those of the full wafer scheme, however the reduction of the number of measurements that is made in optimized sampling reduce the metrology tool time by 26% from that required using the current scheme of factory. Therefore, the cost of metrology can be further reduced by applying the proposed optimized sampling map in the routine operations of fab.