Development of 38nm Bit-Lines using Copper Damascene Process for 64-Giga bits NAND Flash

In order to develop high density NAND Flash device, the increased number of cell strings for I page buffer forces to form a long bit-line with low sheet resistance, as well as low parasitic capacitance between bit-lines. In this paper, we secured a copper damascene process to form 38nm bit-lines with 76nm pitch using SADP (Self-Aligned Double Patterning) process. The methods to minimize the sheet resistance and to suppress the parasitic capacitance were explained on NAND Flash device with 38nm node technology.