Effective methodology to make DFM guide line

Design For Manufacturing (DFM) has become an important focusing part in the semiconductor industry as the feature size on the chip goes down below the 0.13um technology. Lots of DFM related ideas have been come up, tried, and adopted for wider process window and higher device performance. As the minimum features are getting shrunk, the design rules also become more complicated, but still not good enough to describe the certain pattern that imposes narrow process window or even failure of device. Thus, these process hot spot patterns become to identify, correct, or remove at the design step. One of the efforts is to support a DFM guide line to the designer or add to conventional DRC rules. However it is very difficult to make DFM guideline because we detect the hot spot pattern and confirm if these patterns is real hot spot or not. In this study, we developed effective methodology how to make DFM guide line. Firstly we use the s oftware, called nanoscope to detect hot spots on post OPC layouts and then make this detected hot spot patter n to test patterns that it can check electrical performance and then we compared with electrical performance a ccording to split condition. It is confirmed this method is very effective to make DFM guide line below the 0. 13um technology.