50nm Gate Length Logic Technology With 9-Layer Cu Interconnects For 90nm Node Soc Applications

A 90 run generation logic technology with Cu / low-k interconnects is reported. 50nm transistors are employed gate oxide with 1.3 nm in thickness and operating at 1.0 V. High speed transistors have drive currents of 870 muA/mum and 360 muA/mum for NMOS and PMOS respectively, while generic transistors have currents of 640 muA/mum and 260 muA/mum respectively. Low power process using high-k gate dielectrics and SOI process are also provided in this technology. The low-k SiOC material with 2.9 in the k value is used for 9 layers of dual damascene Cu / low-k interconnects. The effective k (k(eff)) value of interconnect is about 3.6. Fully working 6-T SRAM cell with an area of 1.1 mum(2) and SNM value of 330mV is obtained. For MIM capacitor, voltage coefficient of capacitance is less than 20 ppm/V.