Access Transistor Design And Optimization For 65/45nm High Performance Soi Edram
2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAM（2008）
Abstract
A 65nm prototype embedded DRAM macro on partially depleted SOI (PD-SOI) substrate capable of < 2.Ons latency and the enabling cell technology have been described previously [1,2]. In this paper, we focus on the cell design and optimization for best retention and performance which have been extended to the 45nm node.
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Key words
prototypes,design optimization,voltage,silicon on insulator,dielectrics,integrated circuit design,capacitance,manufacturing
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