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Reducing Test Point Overhead with Don't-Cares.

Midwest Symposium on Circuits and Systems(2012)

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摘要
Test points provide additional control to design logic and can improve circuit testability. Traditionally, test points are activated by a global test enable signal, and routing the signal to the test points can be costly. To address this problem, we propose a new test point structure that utilizes controllability don't-cares to generate local test point activation signals. To support the structure, we propose new methods for extracting don't-cares from assertions and finite state machines in the design. Our empirical evaluation shows that don't-cares exist in many designs and can be used for reducing test point overhead.
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关键词
finite state machines,logic design,logic testing,circuit testability,controllability don't-cares,finite state machines,global test enable signal,local test point activation signals,logic design,signal routing,test point overhead reduction
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