Viscoelastic Modeling and Reliability Assessment of Microelectronics Packages

Viscoelastic stress relaxation occurs at operating temperature in underfill materials of flip-chip packages with high power devices. Multi-level finite element analysis is performed to study the impact of the viscoelastic relaxation on package reliability. The stress simulations reveal that the relaxation in underfill material leads to higher stress concentration in solder bumps. The failure analysis shows that the induced high stress develops higher crack driving forces. The results demonstrate that the underfill material property such as viscosity can shift failure mode from die corner delamination to near bump delamination. Therefore, the numerical study can be used as a guideline to select underfill material for package reliability improvements.