Modeling capacitance of on-chip coplanar transmission lines over the silicon substrate

The paper presents a semi-analytical technique for modeling capacitance of on-chip coplanar transmission lines over conductive silicon substrate. The focus is put on developing expressions for high frequency capacitance which yield reasonable accuracy. The technique is based on the 2-D approach and results in accurate and efficient expressions accounting for frequency dependent behavior of the silicon substrate, as well as for actual transmission lines geometry.