3DVLSI with CoolCube process: An alternative path to scaling

P Batude,C Fenouilletberanger, L Pasini,V Lu, F Deprat, L Brunet,B Sklenard, F Piegasluce, M Casse,B Mathieu,Olivier Billoint,G Cibrario,O Turkyilmaz,H Sarhan,Sebastien Thuries,L Hutin, S Sollier,J Widiez, L Hortemel, C Tabone,Mp Samson,B Previtali, N Rambal, F Ponthenier,J Mazurier, R Beneyton, M Bidaud, E Josse, E Petitprez,O Rozeau,Michel Rivoire, C Euvardcolnat, A Seignard, F Fournel, L Benaissa,P Coudrain,P Leduc,Jm Hartmann, P Besson,Sebastien Kerdiles, C Bout, F Nemouchi, A Royer, C Agraffeil,Gerard Ghibaudo,Thomas Signamarcheix,M Haond,Fabien Clermidy, O Faynot,M Vinet

Symposium on VLSI Technology-Digest of Technical Papers(2015)

引用 106|浏览46
暂无评分
摘要
3D VLSI with a CoolCube (TM) integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm(2). This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube (TM) technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.
更多
查看译文
关键词
epitaxial growth,annealing,very large scale integration
AI 理解论文
溯源树
样例
生成溯源树,研究论文发展脉络
Chat Paper
正在生成论文摘要