On The Reduction Of The Number Of Coefficient Circuits In A Dtcnn Cell

N A Fernandez,V M Brea,D L Vilarino,D Cabello

PROCEEDINGS OF THE 2006 10TH IEEE INTERNATIONAL WORKSHOP ON CELLULAR NEURAL NETWORKS AND THEIR APPLICATIONS（2006）

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摘要

This paper introduces a methodology to reduce the number of coefficient circuits in a DTCNN cell without penalty at application level. Trade-offs like area-processing time, and some other figures of merit like accuracy,and power dissipation are considered. It is shown that it is possible to obtain efficient implementations with a reduced number of coefficient circuits. Some examples illustrate the proposal.

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关键词

hardware reduction, SIMD, CNN, PLS, trade-off area-time

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