Schottky barrier height tuning using P+ DSS for NMOS contact resistance reduction

Nickel silicide (NiSi) contacts are adopted in advanced CMOS technology nodes as they demonstrate several benefits such as low resistivity, low Si consumption and formation temperature. But a disadvantage of NiSi contacts is that they exhibit high electron Schottky barrier height (SBH), which results in high contact resistance (R-c) and reduces the NMOS drive current. To reduce SBH for NMOS, we used phosphorous (P) ion implantation into NiPt silicide with optimized anneal in order to form dopant segregated Schottky (DSS). Electrical characterization was performed using test structures such as Transmission Line Model, Cross-Bridge Kelvin Resistor, Van der Pauw and diodes to extract R-c and understand the effects of P+ DSS on Phi(n)(B) tuning. Material characterization was performed using SIMS, SEM and TEM analysis. We report similar to 45% reduction in R-c over reference sample by optimizing ion implantation and anneal conditions (spike RTA, milli-second laser anneals (DSA)).