Efficient Full-Chip Qa Tool For Design To Mask (D2m) Feature Variability Verification

Techniques to control Across Chip CD Variation are very important in IC design, since it directly impacts the electrical timing and functionality of the designs. VLSI designs today include a rich variety of electrical devices (different gate oxide thicknesses, different threshold voltages, etc.) to provide the much needed flexibility to the chip designer. These devices occur at different proximities and different densities on a full chip design. In this paper, we describe a method for improving and ensuring design-to-mask (D2M) quality via a quantitative relationship between design specification and full chip tapeout results. This is done by applying a layout profiling technique with the aim of capturing comprehensive representation of the design space, this method ensures the quality of design-to-mask flow prior to release OPC data to mask house.