Realistic Scaling Scenario for Sub-100 nm Embedded SRAM Based on 3-Dimensional Interconnect Simulation( the IEEE International Conference on SISPAD '02)Yasumasa Tsukamoto,Tatsuya Kunikiyo,Koji Nii,Hiroshi Makino,Shuhei Iwade,Kiyoshi Ishikawa,Yasuo Inoue,Norihiko Kotanimag(2003)引用 23|浏览13暂无评分AI 理解论文溯源树样例生成溯源树,研究论文发展脉络Chat Paper正在生成论文摘要