Conformal Deposition of an Insulator Layer and Ag Nano Paste Filling of a Through Silicon Via for a 3D Interconnection

In this study, we reported the feasibility of filling a high-aspect-ratio through silicon via (HAR-TSV) with Ag nano paste for a 3D interconnection. TSVs with aspect ratios of 8:1 similar to 10:1 were fabricated in a deep reactive etching system by using the Bosch process. Then, SiO2 insulators were deposited by using various chemical vapor deposition (CVD) processes, including plasma enhanced CVD oxides, of which precursors were silane (PECVD Oxide) and tetraethoxysilane (PECVD-TEOS), and sub-atmospheric CVD oxide (SACVD oxide). We succeeded in obtaining a SiO2 layer with good step coverage over 80% for all via CD sizes by using SACVD oxidation process. The thickness of SiO2 for the via top and the via bottom were in the range 158.8 similar to 161.5 nm and 162.6 similar to 170.7 nm, respectively. The HAR-TSVs were filled with Ag nano paste by using vacuum assisted paste printing. Then, the samples were cured on a hotplate.at 80 degrees C for 2 min. The temperature was increased to 180 degrees C at a rate of 25 degrees C/min and the samples were re-annealed for 2 min. We investigated the effects for the time of evacuation/purge process and of the vacuum drying on the filling properties. A field emission scanning electron microscope (FE-SEM), X-ray microscope and focused ion beam (FIB) microscope were used to investigate the filling profile of the TSV with Ag nano pastes. By increasing the evacuation/purge time and the vacuum drying time, we could fully fill the TSV was full filled with Ag nano paste and then form a metal plug.