$C$ – $V$ Characteristics in Undoped Gate-All-Around Nanowire FET Array

IEEE Electron Device Letters(2011)

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摘要
Presented in this letter are the C-V data, measured from nanowire capacitors, which have been fabricated by connecting in parallel a large number of identically processed nanowire FETs. The C-V curves were examined over a range from accumulation to inversion with varying frequencies and at different electrode configurations. The gate response of the undoped and floating channel is investigated usi...
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关键词
Logic gates,Capacitance,Silicon,FETs,Nanoscale devices,MOSFET circuits,Arrays
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