A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy

IEEE Journal of Solid-State Circuits(2013)

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摘要
A Bang-Bang Clock and Data Recovery (CDR) with adaptive loop gain strategy is presented. The proposed strategy enhances CDR jitter performance even if jitter spectrum information is limited a priori. By exploiting the inherent hard-nonlinearity of Bang-Bang Phase Detector (BBPD), the CDR loop gain is adaptively adjusted based on a posteriori jitter spectrum estimation. Maximizing advantages of ana...
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关键词
Jitter,Clocks,Timing,CMOS integrated circuits,Bit error rate,Power generation,Cutoff frequency
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