"A Stochastic Algorithm for the Extraction of Partial Inductances in IC Interconnect Structures"

With recent increases in operating frequencies, the modeling and extraction of on-chip inductance is becoming an increasingly significant consideration. The inductance models include the "loop inductance" models and the "partial inductance" models. In this paper, we develop a stochastic solution methodology for the extraction of partial inductances in IC interconnect structures. An important advantage of this approach is that it requires no discretization meshing of either the volume or the surface of the problem domain. As a result, it has very low memory requirements compared to the more conventional deterministic techniques. Another advantage of this approach is that it is inherently parallelizable and a linear increase in speed is expected with the increase in the number of processors. Excellent agreement has been obtained with analytical benchmark solutions.