Gate Induced Drain Leakage Reduction With Analysis Of Gate Fringing Field Effect On High-Kappa/Metal Gate Cmos Technology

We suggest the optimum permittivity for a high-kappa/metal gate (HKMG) CMOS structure based on the trade-off characteristics between the fringing field induced barrier lowering (FIBL) and gate induced drain leakage (GIDL). By adopting the high-kappa gate dielectric, the GIDL from the band-to-band tunneling at the interface of gate and lightly doped drain (LDD) is suppressed with wide tunneling width owing to the enhanced fringing field, while the FIBL effects is degenerated as the previous reports. These two effects from the gate fringing field are studied extensively to manage the leakage current of HKMG for low power applications. (C) 2015 The Japan Society of Applied Physics