A 5 GHz floating point multiply-accumulator in 90 nm dual V/sub T/ CMOS

A 32 b single-cycle floating point accumulator that uses base 32 and carry-save format with delayed addition is described. Combined algorithmic, logic and circuit techniques enable multiply-accumulate operation at 5 GHz. In a 90 nm 7M dual-V/sub T/ CMOS process, the 2 mm/sup 2/ prototype contains 230K transistors and dissipates 1.2 W at 5 GHz, 1.2 V and 25/spl deg/C.