Providing Balanced Mapping for Multiple Applications in Many-Core Chip Multiprocessors

As the number of cores continues to grow in chip multiprocessors (CMPs), application-to-core mapping algorithms that leverage the non-uniform on-chip resource access time have been receiving increasing attention. This paper addresses the looming issue of balancing on-chip packet latencies in the multi-application mapping of chip multiprocessors (CMPs). Specifically, minimizing the maximum on-chip latency is selected as the objective function, which concurrently alleviates imbalance and ensures a small overall average latency. Then the proposed latency balancing mapping problem is formulated, its NP-completeness is proven, and an efficient heuristic for solving the problem is presented. The proposed algorithm, hOBM, utilizes the on-chip traffic characteristics in CMPs and takes into account many variations exhibited among applications. Simulation results show that the proposed algorithm is able to reduce the maximum average packet latency by 11.29% and the standard deviation of on-chip packet latencies by 99.71% among concurrently running applications and, at the same time, incur little overhead in the overall packet latency and power consumption.